This invention relates to a semiconductor memory device, and more particularly, to a MIS-type semiconductor memory device using a SOI (silicon on insulator) element formed on an insulating film.
Density of integration and resultant increase of the memory capacity are important factors for improving the performance of memory LSI using MIS (Metal-Insulator-Semiconductor) type semiconductor elements. Improvement of density of integration has conventionally relied on reducing the size of elements.
SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are well known as memory LSI. In DRAM, one storage cell is made up of a combination of one capacitor for holding an electric charge and one transistor for controlling injection and emission of the electric charge. Therefore, DRAM eliminates the use of transistors in cross connection, which are required in SRAM, thereby can reduce the memory size, and is suitable for enhancing the integration. Actually, therefore, DRAM has moved on toward higher and higher integration.
However, since miniaturization of capacitors was more difficult than miniaturization of transistors, as the integration of LSI progressed, the area occupied by capacitors, which needed a relatively large area, relatively increased, and this have made it difficult to form capacitors ensuring reliable operation. Beside this, because DRAM needs the process of producing capacitors as an additional process, it has complicated the manufacturing process and has caused a longer period of time for the manufacture, higher cost and lower ratio of non-defective products (production yield).
For the purpose of overcoming those problems attendant to the presence of capacitors, various proposals have been presented. A memory cell employing a SOI (Silicon On Insulator) structure in which an element is formed on an insulating film is known as one of such proposals. This memory cell uses a partial depletion type SOI element and is based on the principle of having an electric charge accumulated in or exhaled from the floating body region of the element in response to the stored data to vary the threshold voltage of the element such that, upon reading, data is distinguished by detection of the threshold value.
FIG. 13 shows a basic circuit diagram of a memory cell using such a SOI element. The gate of a partial depletion type transistor Tr is connected to a word line WL, one of the source and the drain to a bit line BL, and the other to Vss.
Behaviors of the memory cell will be explained below. Here is taken an example using an n-channel MOSFET (nMOSFET).
When data is written in the body region in a floating condition, the word line WL as the gate electrode is set in a high potential (HIGH) state, such as Vcc, and the bit line BL in a HIGH state, also such as Vcc. Then, when a channel current flows, impact ionization occurs, and holes are accumulated in the body region. Additionally, since the diffusion layer connected to the bit line and the pn junction located in the body region are reverse-biased, a leak current in the reverse direction is generated, and this results in increasing the potential of the body region and decreasing the threshold voltage of the element. This status is determined as writing of data “1”, for example.
On the other hand, when the word line is set in a HIGH state, such as Vcc, and the bit line is set in a low potential (LOW) state, such as −Vcc, for example, the diffusion layer connected to the bit line and the pn junction located in the body region are forward-biased. Therefore, holes in the body region flow toward the bit line, and the hole concentration in the body region decreases. As a result, potential of the body region lowers, and the threshold voltage of the element rises. This status is determined as writing of data “0”.
In this manner, it is possible to let the partially depleted transistor change in threshold value in response to the stored data.
This method makes it possible to make up a single memory cell using only one transistor without using a capacitor that has been cumbersome because of the area it occupied, and makes it possible to accomplish higher integration, simplification of the manufacturing process, reduction of the cost, and so forth.
Such configuration, however, invited undesirable flow of a channel current also upon application of −Vcc to a bit line for the purpose of writing data “0”, which made it difficult to efficiently draw out holes of the body region, and therefore involved the problem of taking much time for writing data “0” or rendering the writing unstable.